The present invention relates generally to integrated circuit design, and more particularly to methods and apparatus for operating master-slave latches.
Master-slave latches are employed commonly in integrated circuit design. In a master-slave latch, a master latch latches data in response to a first clock signal, and a slave latch coupled to the master latch latches data (latched by the master latch) in response to a second clock signal. Typically the first and second clock signals are approximately complimentary (e.g., 180 degrees out of phase).
To save power, it is known to operate a master-slave latch in a pulsed mode in which the master latch is held open and the slave latch is pulsed to latch data that passes through the master latch while the master latch is held open. Because the master latch never switches, a pulsed mode of operation significantly reduces power consumption.
While a pulsed mode of operation reduces power consumption, such a mode of operation is susceptible to a number of problems. If the pulse employed to latch data into the slave latch is too wide, the master-slave latch may be susceptible to early mode problems such as race through (e.g., as both master and slave latches are active simultaneously for the duration of the slave latching pulse). Likewise, if the pulse employed to latch data into the slave latch is too narrow, data may not be reliably latched by the slave latch. Accordingly, designing and implementing a pulsed mode of operation for a master-slave latch is difficult, and often requires multiple design and test iterations. Therefore, improved methods and apparatus for operating master-slave latches would be desirable.
In a first aspect of the invention, a method is provided for operating a master latch and a slave latch coupled to the master latch. The method includes the step of attempting to operate the master latch and the slave latch in a first mode in which (1) the master latch is held in an open condition; and (2) the slave latch is pulsed so as to latch data passed through the open master latch. If the master latch and the slave latch do not operate in the first mode, the master latch and the slave latch are operated in a second mode in which (1) a first clock signal is employed to latch data with the master latch; and (2) a second clock signal is employed to latch data latched by the master latch with the slave latch.
In a second aspect of the invention, an apparatus is provided that includes a clock generation circuit adapted to couple to (e.g., drive) a master latch and a slave latch. The clock generation circuit is adapted to operate in a first state in which the clock generation circuit generates (1) a first clock signal for latching data with the master latch; and (2) a second clock signal for latching data latched by the master latch with the slave latch. The clock generation circuit is also adapted to operate in a second state in which the clock generation circuit generates (1) a hold signal for holding the master latch in an open condition; and (2) a pulse signal for directing the slave latch to latch data passed through the master latch while the master latch is held in the open condition by the hold signal. The apparatus further includes a switching circuit coupled to the clock generation circuit and adapted to switch the clock generation circuit between the first state and the second state. Numerous other aspects are provided.
Other features and aspects of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.